SHAPER is a testbed to evaluate Digital Predistortion (DPD) and Crest Factor Reduction (CFR) solutions for microwave power amplifiers. The testbed, which is fruit of a close collaboration with UPC University, comprises a Matlab Testbench that includes the baseband TX, RX, DPD & CFR blocks and is able to interface the laboratory instruments (configure, control and send/receive waveform data).
The high-end instrumentation together with a modular and HW architecture aware design of the Matlab TX and RX blocks make the testbed really versatile and suitable to experiment with flexible multi-band and/or channel aggregation signal configurations, data rates, bandwidths, modulation depths and RF frequencies by only changing the configuration parameters for a given PHY development and frequency plan.
These features make SHAPER an ideal candidate to evaluate DPD and CFR techniques for next generation wideband wireless applications, multi-band scenarios or highly demanding solutions such as wireless backhauling.
- SHAPER test setup
- Full results traceability and repeatibility
- Ultra wide performance (BW, RF frequency)
- TX (AWG): Up to 24 Gsa/s, 9 GHz analog BW
- RX (DPO): Up to 100 Gsa/s, 20 GHz analog BW
- Extract and validate PA behavioural models
- Simulate & benchmark DPD & CFR techniques
- Targeting multiple PA technologies
- Supporting multiple wireless standards
- Emulate HW constraints before implementation
- Relevant project developments:
- Energy efficient solutions for microwave wideband power amplifiers (with AVIAT Networks): The objective of this project (performed in collaboration with UPC) was to improve the performance and energy efficiency of RF/microwave transmitters for next generation wireless backhaul solutions by incorporating different kinds of signal processing techniques at the transmitter baseband. The specific technical details are confidential.
- Next development stages towards a real-time FPGA implementation:
- 1st stage: Matlab testbench interfacing COTS FPGA-A/D-D/A boards (on-going).
- 2nd stage: Challenging RTL design for DPD bandwidth > 500 MHz (Real-time FPGA).
- Team members:
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