Developed PoCs

Timeline

2019
  • Topic: Run-time partial reconfiguration of programmable logic (PL) functions and processing system (PS) firmware developed for agile SDR systems featuring FPGAs and FPGA MPSoCs devices as hardware accelerators.
  • Projects: ORCA (H2020, third party subcontracted by Imec under project ReproRun), 5G-TRIDENT (national).
  • SDR platforms: i) Xilinx ZC706 Evaluation Kit combined with the Analog Devices AD-FMCOMMS-3 evaluation board, ii) Ettus Research USRP X310 platform.
  • Background:
    • References: to be added soon.
    • VIDEO: to be added soon.
    • Figure 4.
2018
  • Topic: Implementation of the digital front-end functions (crest factor reduction and digital predistortion) for multi-antenna 5G remote radio heads, generating and looping back CPRI traffic on the same board.
  • Project: ITERATE (industrial, TTI, Spain).
  • SDR platform: Xilinx ZCU102 Evaluation Kit combined with the Analog Devices AD-FMCDAQ2 evaluation board.
  • Background:
    • No further information can be disclosed.
2017
  • Topic: Propriety implementation of the DL LTE PHY-layer (eNB and UE), which was integrated with a purpose-built customization of CTTC’s EXTREME® testbed. The latter hosted a suitably modified version of the ns-3 LTE extensions (LENA) (e.g., without LENA’s native PHY-layer, adding a custom PHY-MAC interface, separating the software processes of the eNB, UE and EPC). This joint end-to-end testbed added over-the-air testing capabilities to LENA and helped to validate among others the PHY-MAC and PHY-RF RAN functional splits (FS 6 and FS 8 respectively) and also a number of different KPIs.
  • Projects: Flex5Gware (H2020), AEThER (national).
  • SDR platform: Xilinx ZC706 Evaluation Kit combined with the Analog Devices AD-FMCOMMS-3 evaluation board.
  • Background:
2014-2016
2012-2013
  • Topic: Interference mitigation in heterogeneous networks. Real-time FPGA implementation of a Macro BS and UE pair (primary transmission) operating in the same band with a Femto eNB and UE pair (secondary transmission). The customization of GEDOMIS® included RF up and down conversion and different channels applied to the real-time channel emulator. The interference detection scheme made use of different sub-bands (i.e., the 20 MHz spectrum was divided in two 10 MHz bands).
  • Projects: BeFEMTO (FP7), NEWCOM# (FP7), GRE3N (national).
  • SDR platform (legacy): Lyrtech ADP platform combined with two Agilent E4438C VSGs (RF up-conversion) & the Mercury Computer Systems RF 3000T (4 channels phase-coherent RF down-conversion).
  • Background:
2009-2012
  • Topics: WiMAX and LTE PHY-layer real-time PoCs featuring MIMO, SIMO and MISO antenna configurations. The baseband processing was entirely implemented in FPGA devices.
  • Projects: MIMOWA, (national, MEDEA+), BuNGee (FP7), GEDOMIS-ADCOMM (regional), BeMImoMAX (industrial, Lyrtech/Nutaq Inc., Canada).
  • SDR platforms (legacy): i) Lyrtech ADP platform combined with two Agilent E4438C VSGs (RF up-conversion) & the Mercury Computer Systems RF 3000T (4 channels phase-coherent RF down-conversion), ii) Nutaq uSDR420 platform.
  • Background:

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Gallery: figures, block diagrams & photos

 

ReproRun

Figure 4: Run-time partial reconfiguration of PL-based  DSP functions and PS-based firmware (both fetched through TFTP from a remote host), a concept that could be applied in NFV and other 5G key radio technologies. This PoC was developed in the framework of the H2020 ORCA project (ReproRun).

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Flex5Gware_demo
Figure 5: Functional Splits 6 (PHY-MAC) and 8 (PHY-RF) using a proprietary real-time FPGA implementation of the eNB and UE L1 and the ns-3 extensions for LTE (LENA) for the upper layers and EPC (project H2020 Flex5Gware).

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Flex5Gware
Figure 6: Measurement campaign for the Flex5Gware project in order to assess the energy consumption KPI in FPGA devices RF transceiver ICs and Ethernet ICs.

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Emphatic
Figure 7: The setup of GEDOMIS® in the FP7 EMPhAtiC project. Flexible broadband FBMC transmitter (real-time FPGA implementation) coexisting with TETRAPOL transmissions at the 400 MHz band.

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GEDOMISFigure 8: Flexible broadband FBMC transmitter (real-time FPGA implementation) coexisting with TETRAPOL transmissions at the 400 MHz band. Full PoC setup @CTTC.

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ETSI Emphatic

Figure 9: Flexible broadband FBMC transmitter (real-time FPGA implementation) coexisting with TETRA transmissions at the 400 MHz band. ETSI workshop on Reconfigurable Radio Systems, 3-4 December 2014, Sophia Antipolis, France.

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BeFEMTO_resumed
Figure 10: FPGA-based baseband system developed and experimentally validated using  a GEDOMIS® SDR customization together and the real-time multi-channel emulator, in order demonstrate an interference mitigation scheme applied to HetNets.

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GEDOMIS_demo_Madrid

Figure 11: Demonstration of a 2×2 MIMO WiMAX Tx & Rx, real-time FPGA PHY implementation. European Nanoelectronics Forum 2010, Nov. 16-17, Madrid, Spain.

GEDOMIS remote demo (Berlin)

Figure 12: Remote access of the same demonstration. DSPecialists GmbH commercial event, 11-13 May 2011, Berlin, Germany.

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